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Polyphase Interpolation Filter
Signal
FIRO
DATAO_VALID
In/Out
Out
Out
Port Width, Bits
DATA_WIDTH +
COEF_WIDTH +
ceiling(log 2 (TAPS/INTRP_F
ACTOR))
1
Description
Interpolated data output. The filtered data appears on this port. It is
a full precision output. For example, at 12-bit data, 15-bit
coefficients, and 150 taps, L = 10 the output width = 12 + 15 +
ceil(log 2 15) = 12 + 15 + 4 = 31 bits.
Output data valid. Active high. Indicates that a new output data
sample is present at the FIRO port.
READY
Out
1
Active high. The core is ready to accept a fresh input data sample.
Can optionally be used to simplify interface between a data source
and the filter.
RCLK
In
1
A downstream device is ready to accept another interpolated
sample from the filter. The optional signal helps to lower CoreFIR
output rate to match the interpolated sample recipient throughput.
In case the recipient is not ready to accept another filtered sample,
it deactivates the RCLK signal until it is ready. If the recipient is
always ready to accept the filter output sample rate, the signal must
be activated. This happens automatically if the RCLK pin is not
connected to user circuitry.
Figure 35 and Figure 36 show examples of the core pinout in Constant and Reloadable coefficient modes
and Figure 37 shows Multiple coefficient set mode.
CoreFIR
input data
input data valid
DATAI
DATAI_VALID
FIRO
FIRO_VALID
output data
output data valid
COEFI
COEFI_VALID
COEF_SEL
Optional
refresh coefficient set
COEF_REF
COEF_REF_DONE
Optional flag of set
loading completion
COEF_ON
Optional confirmation
a recipient is ready
clock
synch reset
asynch reset
RCLK
CLK
RSTN
NGRST
READY
Optional ready for a new
input data sample
Figure 35 · Constant Coefficient Configuration
40
CoreFIR v8.5 Handbook
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